Ferroelectric random-access memories (FRAM) typically include a grid or an array of storage elements or cells, each including at least one ferroelectric capacitor and one or more associated transistors to select the cell and control reading or writing thereto. When an external electric field is applied across a ferroelectric material of a ferroelectric capacitor in the cell, dipoles in the material align with the field direction. After the electric field is removed, the dipoles retain their polarization state. Data is stored in the cells as one of two possible electric polarizations in each data storage cell. For example, in a one transistor-one capacitor (1T1C) cell, a “1” may be encoded using a negative remnant polarization, and a “0” may be encoded using a positive remnant polarization.
The ferroelectric capacitor in an FRAM cell typically includes a ferroelectric material, such as lead zirconate titanate (PZT) between an upper electrode and a lower electrode. The transistors in the cells are typically metal-oxide-semiconductor (MOS) transistors fabricated using a standard or baseline complimentary-metal-oxide-semiconductor (CMOS) process flows, involving the formation and patterning of conducting, semiconducting, and dielectric materials. The composition of these materials, as well as the composition and concentration of processing reagents, and temperature used in such a CMOS process flow are stringently controlled for each operation to ensure that the resultant MOS transistors function properly. Materials and processes typically used to fabricate the ferroelectric capacitor differ significantly from those of the baseline CMOS process flow, and can detrimentally impact the MOS transistors.
Moreover, stringent design rules may be utilized when fabricating interconnect layers to interface the ferroelectric components with CMOS layers, as the potential for defects and errors in the manufacturing process (e.g., misalignments) increases with the number of subsequent processing steps.